The increasing prominence of portable systems and the need to limit power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The driving forces behind these developments are portable device applications requiring low power dissipation and high throughput, such as note book computers, Portable Communication Devices and Personal Digital Assistants (PDA’s). In most of there cases, the requirements for low power consumption must be met along with equally demanding goals of high chip density and high throughput. The average power consumption in conventional CMOS digital circuits can be expressed as the sum of three main components, namely,(i)the dynamic(switching) power consumption, (ii)the short-circuit power consumption, and (iii)the leakage power consumption.

New logic CMOS families using pass transistor circuit techniques have recently been proposed with the objective of improving speed and power consumption. This logic (in most cases) passes the charge between the nodes rather than charging the nodes from VDD and then discharging them to GND. This feature contributes to less power being used as compared to the regular CMOS. The Double Pass-Transistor Logic (DPL), developed by Hitachi demonstrated a 1.5nS 32-bit ALU and 4.4nS 54-bit multiplier in 0.25 um technology. However, DPL has not yet been fully adopted because of its high transistor count. The objective of the new logic gates and the synthesis method developed for pass-transistor logic is to minimize the number of transistors used in DPL and preserve the speed of the logic.

II. New Logic Gates

The new logic gate represents an improvement over DPL family achieved by the elimination of the redundant branches and rearrangement of signals. This simplification, illustrated in Fig preserves

the advantages of DPL gates which are:

a) Compensation of speed degradation due to the use of pMOS transistors.

b) Straightforward full swing operation. This simplification is achieved by in three steps:

A. Elimination of the redundant branches:

This simplification is achieved by eliminating the redundant branches (shown in shaded area) from DPL. Most of the pull up and pull down transition times, in the resulting configuration,

surpass those of the DPL gates. However, the improved gate has some undesirable input configurations in which the current path is supplied by a single transistor instead of a double pass transistor (as in the case in DPL), making this transition time worse. To avoid degradation of delay due to the use of the just one pMOS transistor, the particular transistor width is increased. The elimination of redundant branches is illustrated in Fig. The resulting two halves (which constitute the gate) are not of the same speed. The faster half is NAND (60 pS) and the slower is AND (70 pS), which is still being faster thanDPL (75 pS).