HP Fully-Depleted CMOS Tri Gate Transistor

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5–2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools.

Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three–dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose aviable alternative to bulk transistors in the near future.

NE of the challenges facing continued scaling of fully-depleted (FD) SOI transistor is the scaling of the dimensions of the active silicon channel region. In the case of single-gate FDSOI devices, the silicon body thickness ( ) needs to be about a third to a half of the electrical gate length in order to maintain full substrate depletion under gate control ([1], [2] – see Fig. 1). Scaling this device to 30 nm gate length dimensions, for example, requires a 3- thickness uniformity of 1 nm on a silicon film thickness of 10 nm, which is presently hard to achieve.

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Raj J

HP Fully-Depleted CMOS Tri Gate Transistor
3 years ago