The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore’s Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years.

Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques. 

As manufacturing processes are constantly moving toward very deep submicron (VDSM) technology, the device feature size of CMOS technology is continuously scaling down. However, this trend also makes leakage power play a dominant role in system power dissipation. To tackle the problem of leakage power, various emerging low-power devices have been developed in recent years. Among them, the single-electron transistor (SET) is regarded as one of the most promising devices since it can operate with only few electrons at room temperature. However, a SET device is suffering from low transconductance and degraded output resistance since only few electrons are involved in a switching operation. Consequently, a SET-based circuit must be designed in conjunction with non-CMOS logic architectures. A binary decision diagram(BDD) based logic structure has been proposed as a feasible approach for realizing logic functions using SETs.

Since BDD is an alternate representation of the truth table, any Boolean function can be implemented through a proper mapping onto a hexagonal nanowire network controlled by Schottky wrap-gates. A BDD-based hexagonal nanowire network can be assembled using a set of node devices. Each node device has one entry branch and two exit branches; messenger electrons arrive via the entry branch and then leave through either the left exit branch or the right one depending on the control variable of the wrap-gate. An exit branch is a segment of SET-controlled nanowire, and has four operating modes in terms of its conductivity: open, short, active-high, and active-low.